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[Other resource] ethernet.tar

Description: 以太网10/100M IP核Verilog源码，可综合。-IP Ethernet 10/100 nuclear Verilog source can be integrated.
Platform: | Size: 934772 | Author: 箫勇天 | Hits:

[Other resource] ETHERNET

Description: 具备GMII接口和ARP协议功能的千兆以太网控制器。经过Xilinx SPATAN-III FPGA验证, Verilog描述
Platform: | Size: 69619 | Author: winwalk | Hits:

[ARM-PowerPC-ColdFire-MIPS] ethernet_verilog

Description: 这是一个很好的Verilog 编写的8位RISC CPU源码（可做为MCU），并且包括完整的C 语言的测试代码。-This is a very good preparation Verilog 8-bit RISC CPU source (available as MCU), and includes a complete C language test code.
Platform: | Size: 78848 | Author: 张念华 | Hits:

[Mathimatics-Numerical algorithms] macmiim

Description: 一个关于以太网MAC核和介质无关接口的原代码,希望对大家有帮助!-an Ethernet MAC on the nuclear medium and unrelated to the original interface code, we want to help!
Platform: | Size: 61440 | Author: 王平 | Hits:

[VHDL-FPGA-Verilog] MAC

Description: 10M/100M以太网mac子层802.3协议的源代码，包括半双工和全双工。-Mac sublayer 10M/100M Ethernet 802.3 protocol source code, including half-duplex and full duplex.
Platform: | Size: 122880 | Author: fiercewind | Hits:

[Crack Hack] crc

Description: 用于10M，100M，1000M以太网的并行CRC算法，有别于一般的CRC算法。verilog描述-For 10M, 100M, 1000M Ethernet parallel CRC algorithm, the CRC algorithm is different from the ordinary. Verilog Description
Platform: | Size: 1024 | Author: winwalk | Hits:

[VHDL-FPGA-Verilog] ethernet_tri_mode_rtl.tar

Description: verilog实现的异步UART代码，包括发送模块、接收模块，波特率可配置，另附PC机的c代码-Verilog realize asynchronous UART code, including the transmission module, receiver module, the baud rate can be configured, an additional PC-c code
Platform: | Size: 38912 | Author: | Hits:

[VHDL-FPGA-Verilog] DM9000A

Description: Verilog 编写的网卡DM9000A的IP核，altera公司寄的DE2系统中的源程序核-Verilog prepared DM9000A the IP core network card, altera company sent DE2 System source of nuclear
Platform: | Size: 16384 | Author: zhyy | Hits:

[VHDL-FPGA-Verilog] ethernet_tri_mode.tar

Description:
Platform: | Size: 740352 | Author: hrui | Hits:

[Windows Develop] SDH

Description: 他是一个SDH上行代码，有八个模块组成的，能够传输以太网的数据 -He is an SDH uplink code, there is composed of eight modules, Ethernet can transmit data
Platform: | Size: 6144 | Author: 丁勇良 | Hits:

[VHDL-FPGA-Verilog] MAC

Description: Verilog code for MAC
Platform: | Size: 1053696 | Author: dheeru | Hits:

[Other] ethernet_controller

Description: 以太网控制器MAC的verilog代码，已经过验证，可以用。-Ethernet Controller
Platform: | Size: 90112 | Author: 李阳 | Hits:

[VHDL-FPGA-Verilog] FPGAcontrolDM9000AuseVerilog

Description: verilog控制以太网发送程序的实现，用于控制以太网发送-verilog control program for sending Ethernet implementation, used to control the Ethernet to send
Platform: | Size: 4096 | Author: 李振华 | Hits:

[Other] FPGA-DM9000A

Description: FPGA控制DM9000A进行以太网数据收发的Verilog实现-FPGA control DM9000A for Verilog realization of Ethernet data sent and received
Platform: | Size: 2658304 | Author: qmy | Hits:

[VHDL-FPGA-Verilog] xge_mac_latest.tar

Description: Ethernet 10GE MAC 以太网10G的MAC Verilog代码实现-Ethernet 10GE MAC
Platform: | Size: 828416 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] crc_eth

Description: Verilog code to add a CRC field at the end of an ethernet frame.
Platform: | Size: 2048 | Author: caracol | Hits:

[VHDL-FPGA-Verilog] 101259356ethernet

Description: etherent testbeanch by using verilog hdl
Platform: | Size: 1016832 | Author: weike | Hits:

[VHDL-FPGA-Verilog] ethernet-verilog

Description: 非常详细的千兆以太网MAC verilog代码，可以供硬件设计时有关网络的开发参考-Very detailed Gigabit Ethernet MAC verilog code, can be used for hardware design of the network to develop a reference
Platform: | Size: 704512 | Author: 瞿鑫 | Hits:

[VHDL-FPGA-Verilog] 以太网控制器Verilog源码(含有MAC,MII接口)

Description: 以太网控制器Verilog源码(含有MAC,MII接口)(Ethernet controller Verilog source code (including MAC, MII interface))
Platform: | Size: 71680 | Author: 天地孤影i | Hits:

[VHDL-FPGA-Verilog] 10GE Ethernet

Description: 10GE Ethernet FPGA VHDL verilog
Platform: | Size: 610226 | Author: 104758548@qq.com | Hits:
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